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| CXG7003FN Power Amplifier/Antenna Switch + Low Noise Down Conversion Mixer for PHS Description The CXG7003FN is a MMIC consisting of the power amplifier, diversity antenna supported switch and low noise down conversion mixer. This IC is designed using the Sony's GaAs J-FET process featuring a single positive power supply operation. Features * Operates at a single positive power supply: VDD = 3V * Diversity antenna supported switch * Small mold package: 26-pin HSOF Absolute Maximum Ratings 6 1.5 550 3 V V mA W VCTL 6 V VDD PRF 6 10 V dBm 150 -35 to +85 -65 to +150 C C C Recommended Operating Conditions 2.7 to 3.3 V VCTL (H) 2.9 to 3.3 VCTL (L) 0 to 0.2 V V Notes on Handling GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E04401-PS CXG7003FN Block Diagram and External Circuit 2.2nH PIN 14 13 100pF 15 12 2.2nH VDD1 1nF VDD2 1nF VDD3 10nF 18nH 16 1nF 17 30pF 18 9 100pF 19 8 30pF (RX) 30pF VCTL2 100pF (RFIN) 10nH 6.8nH 23 13pF 24 25 100nF VDD (IF AMP, MIX) 1nF 26 82nH 5pF 1 3 VDD (LO AMP) LOIN 22 10pF 3.9nH 4 13pF 1nF VDD (RF AMP) 5 21 6 20 7 30pF ANT1 ANT2 10 30pF VCTL1 11 1pF (TX) (POUT) VGG 18nH 1.8nH 2 18pF 1nF IFOUT Pin Configuration PIN 14 GND 15 VDD1 16 VDD2 17 VDD3 18 GND 19 RX 20 VCTL2 21 RFIN 22 CAP 23 GND 24 CAP 25 IFOUT/VDD (IF AMP, MIX) 26 13 VGG 12 CAP 11 POUT 10 TX 9 8 7 6 5 4 3 2 1 VCTL1 ANT2 ANT1 GND GND VDD (RF AMP) GND VDD (LO AMP) LOIN -2- CXG7003FN Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Symbol LOIN GND GND GND ANT1 ANT2 VCTL1 TX POUT CAP VGG PIN GND VDD1 VDD2 VDD3 GND RX VCTL2 RFIN CAP GND CAP IFOUT/VDD (IF AMP, MIX) Local signal input pin GND pin GND pin GND pin Antenna switch pin. This pin is ANT1-Tx or ANT1-Rx by setting of VCTL1 and VCTL2. Antenna switch pin. This pin is ANT2-Tx or ANT2-Rx by setting of VCTL1 and VCTL2. Antenna switch control 1 pin Tx pin. Signal is input to antenna switch during ANT-Tx. Power amplifier output pin Connection pin of external capacitor (for noise elimination) Gate voltage adjustment pin of power amplifier (first stage, middle stage, rear-end FET) Signal input pin to power amplifier GND pin VDD1 pin of power amplifier (first stage FET) VDD2 pin of power amplifier (middle stage FET) VDD3 pin of power amplifier (rear-end FET) GND pin Rx pin. ANT input signal is output to this pin during ANT1-Rx or ANT2-Rx. Antenna switch control 2 pin RF signal input pin External capacitor connection pin. This pin is connected to LNA FET source. RF amplifier characteristic is optimized during 1.9GHz by the capacitor of 13pF (Typ.). GND pin External capacitor connection pin. IF amplifier distortion is improved by this capacitor. IF output and IF AMP, MIX VDD VDD (LO AMP) VDD pin of local amplifier VDD (RF AMP) VDD pin of RF amplifier Description -3- CXG7003FN Electrical Characteristics These specifications are when the Sony's recommended evaluation board shown on page 8 is used. 1. Control Pin Logic for Antenna Switch Conditions of control pins VCTL1 = 3V, VCTL2 = 0V VCTL1 = 0V, VCTL2 = 3V ANT1 - TX ANT2 - RX ON OFF ANT2 - TX ANT1 - RX OFF ON 2. Power Amplifier Block + Antenna Switch Transmitter Block These specifications are common to the ANT1 transmission and ANT2 transmission. Unless otherwise specified: VDD = 3V, IDD = 150mA, POUT = 20.2dBm, f = 1.9GHz When ANT1 transmission: VCTL1 = 3V, VCTL2 = 0V When ANT2 transmission: VCTL1 = 0V, VCTL2 = 3V (Ta = 25C) Item Current consumption Gate voltage adjustment value Output power Power gain Adjacent channel leak power ratio (600 100kHz) Adjacent channel leak power ratio (900 100kHz) Occupied bandwidth 2nd-order harmonic level 3rd-order harmonic level IDD VGG POUT GP ACPR600kHz ACPR900kHz OBW -- -- Measured with the ANT pin Measured with the ANT pin Measured with the ANT pin Measured with the ANT pin Measured with the ANT pin Measured with the ANT pin 0.04 20.2 36 40 -63 -70 250 Symbol Measurement conditions Min. Typ. Max. Unit 150 0.6 mA V dBm dB -55 dBc -60 dBc 275 kHz -25 dBc -25 dBc -4- CXG7003FN 3. Antenna Switch Receiver Block + Low Noise Down Conversion Mixer Block These specifications are common to the ANT1 reception and ANT2 reception. Unless otherwise specified: VDD = 3V, RF1 = 1.90GHz/-35dBm, LO = 1.66GHz/-15dBm When ANT1 reception: VCTL1 = 0V, VCTL2 = 3V When ANT2 reception: VCTL1 = 3V, VCTL2 = 0V (Ta = 25C) Item Current consumption Conversion gain Noise figure Input IP3 Image suppression ratio 1/2 IF suppression ratio 2 x LO-IF suppression ratio 2 x LO+IF suppression ratio LO to ANT leak PLK IDD GC NF IIP3 IMR 1/2IFR -- -- Symbol Measurement conditions When no signal When a small signal When a small signal 1 RF2 = 1.42GHz/-35dBm RF2 = 1.78GHz/-35dBm RF2 = 3.08GHz/-35dBm RF2 = 3.56GHz/-35dBm 17 -17 25 41 39 34 Min. Typ. Max. Unit 5.5 19.5 4.4 -12 40 47 45 65 -50 5.5 7.5 mA dB dB dBm dBc dBc dBc dBc -40 dBm 1 Conversion from IM3 suppression ratio during RF1 = 1.9000GHz/-35dBm and RF2 = 1.9006GHz/-35dBm input. -5- CXG7003FN Example of Representative Characteristics 1. Power Amplifier + Antenna Switch Transmitter Block (f = 1.9GHz, Ta = 25C) POUT, ACPR600kHz vs. PIN VDD = 3V, VGG = const., IDD = 150mA (@POUT = 20.2dBm), PIN = var. When ANT1 transmission: VCTL1 = 3V, VCTL2 = 0V When ANT2 transmission: VCTL1 = 0V, VCTL2 = 3V The data shown below is common to ANT1 and ANT2. 25 -40 POUT, ACPR600kHz vs. VDD VDD = var., VGG = const., IDD = 150mA (@VDD = 3V, POUT = 20.2dBm), PIN = -19.7dBm When ANT1 transmission: VCTL1 = 3V, VCTL2 = 0V When ANT2 transmission: VCTL1 = 0V, VCTL2 = 3V The data shown below is common to ANT1 and ANT2. 23 -40 ACPR600kHz - Adjacent channel leak power ratio [dBc] 20 POUT - Output power [dBm] POUT 15 -45 22 POUT - Output power [dBm] POUT 21 -45 -50 -50 10 ACPR600kHz 5 -55 20 -55 -60 19 ACPR600kHz -60 0 -65 18 -65 -5 -40 -35 -30 -25 -20 -15 -70 -10 17 2.0 2.5 3.0 3.5 4.0 4.5 -70 5.0 PIN - Input power [dBm] VDD - Supply voltage [V] Gp, ACPR600kHz vs. IDD VDD = 3V, VGG = var., IDD = var., PIN = var., POUT = 20.2dBm When ANT1 transmission: VCTL1 = 3V, VCTL2 = 0V When ANT2 transmission: VCTL1 = 0V, VCTL2 = 3V The data shown below is common to ANT1 and ANT2. -40 42 41 Gp - Power gain [dB] GP 40 -45 -50 39 ACPR600kHz 38 -55 -60 37 -65 36 100 120 140 160 180 200 -70 220 IDD - Current consumption [mA] ACPR600kHz - Adjacent channel leak power ratio [dBc] -6- ACPR600kHz - Adjacent channel leak power ratio [dBc] CXG7003FN 2. Antenna Switch Receiver Block + Low Noise Down Conversion Mixer (Ta = 25C) GC, NF vs. PLO VDD = 3V, RF1 = 1.90GHz/small signal, LO = 1.66GHz When ANT1 reception: VCTL1 = 0V, VCTL2 = 3V When ANT2 reception: VCTL1 = 3V, VCTL2 = 0V The data shown below is common to ANT1 and ANT2. 22 5.50 POUT - IF output power, PIM3 - 3rd-order intermodulation power [dBm] POUT, PIM3 vs. PIN VDD = 3V, RF1 = 1.9000GHz, RF2 = 1.9006GHz, LO = 1.66GHz/-15dBm When ANT1 reception: VCTL1 = 0V, VCTL2 = 3V When ANT2 reception: VCTL1 = 3V, VCTL2 = 0V The data shown below is common to ANT1 and ANT2. 20 21 GC - Conversion gain [dB] 5.25 GC NF - Noise figure [dB] 0 POUT -20 20 5.00 19 4.75 -40 PIM3 -60 18 NF 17 4.50 4.25 -80 Input IP3 -100 -50 -40 -30 -20 -10 0 16 -25 4.00 -20 -15 -10 -5 0 PLO - Local input [dBm] PIN - RF input power [dBm] Input IP3, PLK vs. PLO VDD = 3V, RF = 1.90GHz/-35dBm, LO = 1.66GHz When ANT1 reception: VCTL1 = 0V, VCTL2 = 3V When ANT2 reception: VCTL1 = 3V, VCTL2 = 0V Input IP3 is common to ANT1 and ANT2. -10 Input IP3 -12 -35 -30 PLK - LO to ANT leak level [dBm] Input IP3 [dBm] -14 -40 -16 ANT1 -18 -45 -50 -20 ANT2 -22 -25 -55 -60 -20 -15 -10 -5 0 PLO - Local input [dBm] -7- CXG7003FN Recommended Evaluation Board CXG7003FN Via Hole PAIN VGG ANT2 VDD_PA VCTL1 VCTL2 VDD_LNA VDD_LO IFOUT VDD_IF LOIN ANT1 Via Hole Glass fabric-base epoxy board (4 layers) Thickness between layers 1 and 2: 0.2mm Dimensions: 50mm x 50mm VCTL2 VDD (PA) VDD (LO) VCTL1 (Open) VGG VDD (IF) VDD (LNA) Enlarged Diagram of External Circuit Block C8 L6 C8 L2 C7 C1 L2 C8 C9 L6 C6 L1 C6 C7 C6 C6 L1 = 1.8nH L2 = 2.2nH L3 = 3.9nH L4 = 6.8nH L5 = 10nH L6 = 18nH L7 = 82nH C1 = 1pF C2 = 5pF C3 = 10pF C4 = 13pF C5 = 18pF C6 = 30pF C7 = 100pF C8 = 1nF C9 = 10nF C10 = 100nF C7 L5 L4 C4 C10 C6 C3 C4 L3 C2 C5 L7 C8 C8 C8 -8- CXG7003FN Package Outline Unit: mm HSOF 26PIN (PLASTIC) 0.9 0.1 5.6 0.05 A 26 14 0.08 S 5.5 4.2 3.8 0.05 4.4 0.1 (1.5) (0.7) 0.5 1 0.4 0.07 M S A 13 S 0.2 4.4 0.2 Solder Plating 0.2 0.05 B + 0.05 0.14 - 0.03 NOTE: Dimension " " does not include mold protrusion. DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE HSOF-26P-01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.06g LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18m (0.2) + 0.05 0.2 0 0.4 -9- (1.75) Sony Corporation 0.45 0.15 |
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